Infrared image sensor component manufacturing method

ABSTRACT

A method includes epitaxially growing a first III-V compound layer over a semiconductive substrate. A second III-V compound layer is epitaxially grown over the first III-V compound layer. A source/drain contact is formed over the second III-V compound layer. A gate structure is formed over the second III-V compound layer. A pattern is formed shielding the gate structure and the source/drain contact, in which a portion of the second III-V compound layer is free from coverage by the pattern.

RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 15/870,940, filed Jan. 13, 2018, now U.S. Pat. No. 10,453,881, issued Oct. 22, 2019, which is a continuation of U.S. application Ser. No. 15/051,600, filed Feb. 23, 2016, now U.S. Pat. No. 9,871,067, issued Jan. 16, 2018, which claims priority to U.S. Provisional Application Ser. No. 62/256,600, filed Nov. 17, 2015, all of which is herein incorporated by reference in their entireties.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation.

In semiconductor technologies, image sensors are used for sensing a volume of exposed light projected towards the semiconductor substrate. Complementary metal-oxide-semiconductor (CMOS) image sensor devices are widely used in various applications such as digital still camera (DSC) applications. These devices utilize an array of active pixels or image sensor cells, including photodiode elements and MOS transistors, to collect photo energy to convert images to streams of digital data.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A to FIG. 1E are local cross-sectional views of different stages of a method of manufacturing an infrared image sensor component, in accordance with some embodiments of the disclosure.

FIG. 2 is a local cross-sectional view of an infrared image sensor component, in accordance with some embodiments of the disclosure.

FIG. 3A to FIG. 3F are local cross-sectional views of different stages of fabricating an infrared image sensor component, in accordance with some other embodiments of the disclosure.

FIG. 4 to FIG. 11 are local cross-sectional views of an infrared image sensor component, in accordance with different embodiments of the disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The present disclosure is related to an infrared image senor component. The infrared sensor component includes a substrate, a III-V compound layer disposed on the substrate as an active pixel region, and a plurality of transistors formed on the III-V compound layer. The III-V compound layer is made of III-V groups materials, which have wide infrared wavelength coverage, large absorption coefficient in the infrared region, and high carrier mobility. Therefore, the performance of the infrared image sensor component can be improved accordingly.

FIG. 1A to FIG. 1E are local cross-sectional views of different stages of a method of manufacturing an infrared image sensor component, in accordance with some embodiments of the disclosure. Reference is made to FIG. 1A. A III-V compound layer 120 is formed on a substrate 110. The substrate 110 is a semiconductor substrate. In some embodiments, the semiconductor substrate is made of, for example, silicon; a compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or an alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The substrate 110 may optionally include various doped regions, dielectric features, or multilevel interconnects in the semiconductor substrate.

The III-V compound layer 120 is made from the III-V groups in the periodic table of elements. In some embodiments, the III-V compound layer 120 is a single layer having a tuned energy gap. In some other embodiments, the III-V compound layer 120 is a combination of multiple III-V material layers with wide and narrow energy gap. In yet some other embodiments, the III-V compound layer 120 may have gradient energy gap.

The III-V compound layer 120 or each of the layers of the III-V compound layer 120 is made of material selected from a group consisting of In_(w)Al_(x)Ga_(y)As_(z), In_(w)Al_(x)Ga_(y)P_(z), In_(w)Al_(x)Ga_(y)Sb_(z), In_(w)Al_(x)AS_(y)P_(z), In_(w)Al_(x)P_(y)Sb_(z), In_(w)Ga_(x)AS_(y)P_(z), In_(w)Ga_(x)P_(y)Sb_(z), Al_(w)Ga_(x)As_(y)P_(z), Al_(w)Ga_(x)P_(y)Sb_(z), In_(w)As_(x)P_(y)Sb_(z), Al_(w)As_(x)P_(y)Sb_(z), Ga_(w)As_(x)P_(y)Sb_(z), in which w+x+y+z=1. The III-V compound layer 120 can be epitaxially grown by a number of processes including, but not limited to, molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD), also known as metal organic vapor phase epitaxy (MOVPE), using appropriate precursors. The thickness of the III-V compound layer 120 is in a ranged from about 0.1 μm to about 10 μm.

Reference is made to FIG. 1B. At least one transistor 130 is formed on the III-V compound layer 120. The transistors 130 are formed in an array and are arranged corresponding to the pixels of the infrared image senor component 100. In some embodiments, the transistor 130 can be a metal-oxide-semiconductor (MOS) device. Each of the transistors 130 includes a control gate 132 formed on the III-V compound layer 120, and two doped regions 134, and 136 formed in the III-V compound layer 120 and disposed at opposite sides of the control gate 132. The doped regions 134, and 136 may be doped with impurities. The transistor 130 further includes a gate isolation 138 formed between the control gate 132 and the III-V compound layer 120. The transistor 130 further includes sidewalls 135 formed at opposite side surfaces of the control gate 132.

In some embodiments, the transistor 130 is a complementary metal-oxide-semiconductor (CMOS) device. An exemplary method of fabricating the transistor 130 begins at, for instant, forming a photoresist layer on the surface of the III-V compound layer 120. In some embodiments, the III-V compound layer 120 is a P-type layer which includes P-type impurity. The photoresist layer is performed by masking, exposing and developing to define the region for subsequent ion injection, then respectively form a N-type doped regions 134, and 136 in the III-V compound layer 120 by ion injection. The photoresist layer is removed by, such as stripping, after the N-type doped regions 134, and 136 are formed. The doping impurity of forming the N-type doped regions 134, and 136 can be P, As, Si, Ge, C, O, S, Se, Te, or Sb. The doped regions 134, and 136 are generally formed of a low or high concentration impurity region. In some embodiments, the doped regions 134, 136 are regarded as source/drain regions. In some embodiments, the doped region 134 is extended longer than the doped region 136. The N-type doped region 134 and the underlying portion of P-type III-V compound layer 120 may detect incident light.

An isolation layer is further formed on the surfaces of the III-V compound layer 120 by using a low temperature process, in which the isolation layer may be silicon oxide. A conductive layer is further formed on the isolation layer, in which the conductive layer can be doped polycrystalline silicon, tungsten, titanium nitride, or other suitable materials. One or more etching processes are performed to the isolation layer and the conductive layer thereby forming gate isolation 138 and the control gate 132 thereon. Then the sidewalls 135 are formed at the sides of the control gate 132.

The infrared image sensor component 100 further includes at least one shallow trench isolation structure 180. The shallow trench isolation structure 180 is at least formed in the III-V compound layer 120. In some embodiments, the shallow trench isolation structure 180 is formed in the III-V compound layer 120 and in the semiconductor substrate 110. The shallow trench isolation structure 180 is formed next to the doped region 134 to separate the adjacent pixels. The material of the shallow trench isolation structure 180 can be dielectric, such as oxide.

Reference is made to FIG. 1C. A plurality of patterns 140 and a plurality of dielectric layers 150 are sequentially formed on the III-V compound layer 120 and on the transistors 130. The patterns 140 provide functions including wiring and light shielding. The patterns 140 are formed by depositing a conductive layer and etching the conductive layer. The material of the conductive layer may be metal, such as W, Cu, or Co. The dielectric layer 150 is made of insulating material with high transmittance to improve light transmittance. The dielectric layer 150 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-dielectric constant dielectric material or a combination thereof. The dielectric layer 150 can be formed by a deposition process, such as an ALD process, a CVD process, or a PVD process.

The patterns 140 are formed for shielding a portion of the transistors 130 and a portion of the III-V compound layer 120. Namely, only the doped region 134 and a portion of the III-V compound layer 120 are exposed from the patterns 140. The doped region 134 and the exposed portion of the III-V compound layer 120 are utilized as active pixel region 120′ for sensing the light including infrared ray. The active pixel region 120′ receives light to generate and accumulate photocharges, and a logic element (not illustrated) may detect electric signals transmitted from the corresponding active pixel region 120′.

The energy gap of the active pixel region 120′ can be tuned by the composition of the III-V compound layer 120 and the doped region 134. The energy gap of the active pixel region 120′ is tuned corresponding to the wavelength of the incident light such as infrared ray. The active pixel region 120′ absorbs incident light and accumulates charges corresponding to an amount and/or intensity of the light. The active pixel regions 120′ is coupled with the transistors 130. The transistor 130 includes the control gate 132, and doped regions 134, and 136. The doped region 134 and the under lying III-V compound layer 120 construct the active pixel region 120′ for receiving the charges generated by the active pixel region 120′. The charges are transferred to the doped region 136 through the conducted control gate 132. In some embodiments, doped region 136 generally has parasitic capacitance, so charges may accumulate at the doped region 136. The potential of the doped region 136 can be changed by the accumulated charges, and therefore the amount of charges is detected through the change in electric potential of the doped region 136.

In order to prevent light current leakage, the patterns 140 are formed to shield the portion other than the active pixel region 120′. In some embodiments, the patterns 140 are formed covering the control gate 132, and the doped regions 136. The active pixel region 120′ and the doped region 134 are exposed from the patterns 140 to receive the incident light, such as infrared ray.

Reference is made to FIG. 1D. An infrared filter 160 is disposed on the dielectric layer 150. The infrared filter 160 is an infrared ray pass filter which passes infrared light while blocking other wavelengths. In some embodiments, the infrared filter 160 is formed of a material capable of blocking out all light except for the spectrum that falls between 800 nanometers and 1000 nanometers.

Reference is made to FIG. 1E, an optical lens 170 is formed on the infrared filter 160. The optical lens 170 is formed of thermosetting resin and may have a predetermined curvature radius. The curvature radius of the optical lens 170 can be different depending on the depth of the active pixel region 120′, and the wavelength of incident light. The optical lens 170 changes the path of incident light and collects light onto the active pixel region 120′.

Using the III-V compound layer 120 as the active pixel region 120′ may reduce the thickness of the infrared image sensor component 100. Comparing with the embodiments of silicon substrate having p-n junction diodes, the III-V compound layer 120 provides wider infrared response. Namely, the III-V compound material has wider infrared wavelength coverage than the silicon, such that the infrared ray including near infrared ray, and middle infrared ray can be detected by the III-V compound layer 120. Also, the III-V compound material has larger absorption coefficient in the infrared region than the silicon, such that the thickness of the III-V compound layer 120 is thinner than the p-n junction diodes. Furthermore, the III-V compound material provides higher carrier mobility than the silicon, thus the pixel response of the infrared image sensor component 100 using the III-V compound layer 120 is faster than that of using the silicon substrate with p-n junction diodes.

Reference is made to FIG. 2, which a local cross-sectional view of an infrared image sensor component of some embodiments of the disclosure. The transistor 130 may include epitaxy structures 131 and 133 instead of the doped regions 134 and 136. In order to form the epitaxy structures 131 and 133, a plurality of openings are formed at opposite sides the control gate 132 and in the III-V compound layer 120, and then an epitaxy is performed to grow the epitaxy structures 131 and 133 are formed in the openings. The source/drain stressors form at least parts of the epitaxy structures 131 and 133. In the embodiments in which the transistor 130 is an nMOS device, the epitaxy structures 131 and 133 may include silicon phosphorous (SiP), silicon carbide (SiC), or the like. In the embodiments in which the transistor is a pMOS device, the epitaxy structures 131 and 133 may include silicon germanium (SiGe).

The patterns 140 are formed to shield the control gate 132 and the epitaxy structure 133 and to expose the epitaxy structure 131 and a portion of the III-V compound layer 120. The uncovered III-V compound layer 120 can be utilized as active pixel region 120′ to receive the infrared ray and generate photocharges. The epitaxy structure 131 is coupled to the active pixel region 120′, thus the charges are received by the epitaxy structure 131 and is further transferred to the epitaxy structure 133 through the conducted control gate 132, and a logic element (not illustrated) may detect electric signals transmitted from the corresponding active pixel region 120′.

The active pixel regions and the transistors of the infrared image sensor component may have various modifications. For example, FIG. 3A to FIG. 3F show local cross-sectional views of different stages of fabricating an infrared image sensor component, in accordance with some other embodiments of the disclosure. The method begins at FIG. 3A, at least one III-V compound layer is formed on a semiconductor substrate 210. In some embodiments, a first III-V compound layer 220, and a second III-V compound layer 230 are formed on a semiconductor substrate 210.

In some embodiments, the semiconductor substrate 210 is made of, for example, silicon; a compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or an alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The semiconductor substrate 210 may also include various doped regions, dielectric features, or multilevel interconnects in the semiconductor substrate.

The first III-V compound layer 220 and the second III-V compound layer 230 are compounds made from the III-V groups in the periodic table of elements. However, the first III-V compound layer 220 and the second III-V compound layer 230 are different from each other in composition. The first III-V compound layer 220 and the second III-V compound layer 230 can be respectively epitaxially grown by a number of processes including, but not limited to, metal organic chemical vapor deposition (MOCVD), also known as metal organic vapor phase epitaxy (MOVPE), using appropriate precursors. The first III-V compound layer 220 and the second III-V compound layer 230 directly contact each other.

Different composition of III-V compound materials causes the layers to have different energy gaps. An energy gap discontinuity between the first III-V compound layer 220 and the second III-V compound layer 230, along with the piezo-electric effect, creates a very thin layer 240 of highly mobile conducting electrons in the first III-V compound layer 220. The thin layer 240 contributes to a conductive two dimensional electron gas (2DEG) layer near the junction of the two layers. The thin layer 240 (also referred to as the 2DEG layer 240) allows charge to flow through the component.

A third III-V compound layer 250 is further formed on the second III-V compound layer 230. In some embodiments, the third III-V compound layer 250 is a doped III-V compound layer, such a p-type doped GaN layer (also referred to as the doped GaN layer 250). The doped GaN layer 250 can be epitaxially grown by MOCVD using appropriate aluminum, nitrogen and gallium precursors. The aluminum precursor includes trimethylaluminum (TMA), triethylaluminum (TEA), or suitable chemical precursors. Exemplary gallium containing precursors are trimethlgallium (TMG), triethylgallium (TEG) or other suitable chemical precursors. Exemplary nitrogen precursors include, but are not limited to, phenyl hydrazine, dimethylhydrazine, tertiarybutylamine, ammonia, or other suitable chemical precursors. The second III-V compound layer 230 can also be referred to as a barrier layer.

Reference is made to FIG. 3B. The doped third III-V compound layer 250 is patterned for defining at least one doped III-V compound region 252 on the second III-V compound layer 230. The 2DEG layer 240 under the doped III-V compound region 252 is removed. In some embodiments, a mask layer, such as a photoresist layer is formed on the doped third III-V compound layer 250, and the mask layer is patterned by a lithography process to form a plurality of features and a plurality of openings defined by the features on doped third III-V compound layer 250. The pattern of the mask layer is formed according to a predetermined integrated circuit pattern. The lithography process may include photoresist coating, exposing, post-exposure baking, and developing. Then, an etching process is performed to define the doped III-V compound region 252.

A shallow trench isolation structure 212 is formed in the first III-V compound layer 220 and the second III-V compound layer 230 to define an active pixel region of a pixel. In some embodiments, the shallow trench isolation structure 212 is further formed in the semiconductor substrate 210. The shallow trench isolation structure 212 is a dielectric material, such as oxide. The active pixel region is defined between the III-V doped compound region 252 and the shallow trench isolation structure 212.

A dielectric layer 260 is formed on the doped III-V compound region 252 and on the second III-V compound layer 230. The dielectric layer 260 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-dielectric constant dielectric material or a combination thereof. The dielectric layer 260 can be formed by a deposition process, such as an ALD process, a CVD process, or a PVD process. The dielectric layer 260 is further patterned to define a plurality of openings 262 in the dielectric layer 260. The dielectric layer 260 is selectively etched and cleaned to define the openings 262. Exemplary etching processes include sputter etching, reactive gas etching, chemical etching and ion milling. The openings 262 are formed at opposite sides of the doped III-V compound region 252. The openings 262 are led into the second III-V compound layer 230. Namely, the thickness of the second III-V compound layer 230 under the openings 262 is thinner than other portions of the second III-V compound layer 230.

Reference is made to FIG. 3C. A plurality of ohmic metal contacts 270, 272 are formed in the openings 262. The ohmic metal contacts 270, 272 can be formed by depositing a ohmic contact layer on the dielectric layer 260 and in the openings 262, and patterning ohmic contact layer. The deposition process can be sputter deposition, evaporation or chemical vapor deposition (CVD). Exemplary ohmic metals include, but are not limited to, Ta, TaN, Pd, W, WSi2, Ti, Al, TiN, AlCu, AlSiCu and Cu. In some embodiments, the ohmic contacts 270, 272 connect to the second III-V compound layer 230 directly. The ohmic contacts 270, 272 are utilized as a part of drain electrode and a source electrode.

Reference is made to FIG. 3D. The dielectric layer 260 on the III-V doped compound region 252 is etched thereby forming another opening therein. A gate metal stack 274 is further formed in the opening as a gate electrode. The gate metal stack 274 results in a device yielding an enhancement mode (E-mode) device. In the embodiment depicted in FIG. 3D, the gate metal stack 274, the source and drain contacts 270, 272, and the 2DEG layer 240 (as a channel) in the first III-V compound layer 220 are configured as an E-mode transistor 255, which is a normally off device, and when a positive voltage applied to the gate stack for forward bias is great enough, the E-mode transistor is turned on.

Reference is made to FIG. 3E. A plurality of dielectric layers 280 and a plurality of patterns 282 are sequentially formed on dielectric layer 260 and on the transistor 255. The patterns 282 can be conductive patterns and provide functions including wiring and light shielding. The patterns 282 are formed by depositing a conductive layer and etching the conductive layer. The material of the conductive layer may be metal, such as W, Cu, or Co. The dielectric layers 280 are made of insulating material with high transmittance to improve light transmittance. The dielectric layers 280 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-dielectric constant dielectric material or a combination thereof. The dielectric layers 280 can be formed by a deposition process, such as an ALD process, a CVD process, or a PVD process.

The patterns 280 are formed for shielding a portion of the transistors and a portion of the second III-V compound layer 230. Namely, only portions of the III-V compound layer 230 are exposed from the patterns 282. The exposed portion of the second III-V compound layer 230 and the underlying 2DEG layer 240 are utilized as active pixel region 230′ for sensing the light including infrared ray. The active pixel region 230′ receives light to generate and accumulate photocharges, and a logic element (not illustrated) may detect electric signals transmitted from the corresponding active pixel region 230.

The energy gap of the active pixel region 230′ can be tuned by the composition of the first III-V compound layer 220 and the second III-V compound layer 230. The energy gap of the active pixel region 230′ is tuned corresponding to the wavelength of the incident light such as infrared ray. The active pixel region 230′ absorbs incident light and accumulates charges corresponding to an amount and/or intensity of the light. The active pixel regions 230′ is coupled with the transistors 255. The ohmic metal contact 270 is regarded as source and is connected to the active pixel region 230′ for receiving the charges generated by the active pixel region 230′. The charges are transferred to the ohmic metal contact 272 through the conducted control gate 252. In some embodiments, charges may accumulate at the ohmic metal contact 272, which is regarded as drain. The potential of the ohmic metal contact 272 can be changed by the accumulated charges, and therefore the amount of charges is detected through the change in electric potential of the ohmic metal contact 272.

In order to prevent light current leakage, the patterns 282 are formed to shield the portion other than the active pixel region 230′. In some embodiments, the patterns 282 are formed covering the doped III-V compound region 252 and the gate metal stack 274 (e.g., the gate), and the ohmic metal contact 272 (e.g., the drain). The active pixel region 230′ and the ohmic metal contact 270 between the active pixel region 230′and the doped III-V compound region 252 are exposed from the patterns 282 to receive the incident light, such as infrared ray.

Reference is made to FIG. 3F. An infrared filter 290 is disposed on the dielectric layer 280, and an optical lens 292 is formed on the infrared filter 290. The infrared filter 290 is an infrared ray pass filter. The curvature radius of the optical lens 292 can be different depending on the depth of the active pixel region 230′, and the wavelength of incident light. The optical lens 292 changes the path of incident light and collects light onto the active pixel region 230′.

The composition of the III-V compound layers can be modified to tune the energy gap of the III-V compound layers. The composition of the III-V compound layers can be modified by changing the materials of the III-V compound layer, changing the thickness of the III-V compound layer, and/or changing the concentration of the III-V compound layer. Different combinations of the III-V compound layers may result in different response wavelength of the active pixel region. Variations of the combination of the III-V compound layers are discussed in following embodiments.

FIG. 4 to FIG. 11 are local cross-sectional views of an infrared image sensor component, in accordance with different embodiments of the disclosure. Referring to FIG. 4, an infrared image sensor component 400 including an active pixel region 420′ formed on a semiconductor substrate 410, and a transistor 430 coupled to the active pixel region 420′ is provided. The active pixel region 420′ is the portion of a III-V compound layer stack 420 uncovered by the patterns. The III-V compound layer stack 420 includes a plurality of III-V compound layers 422, 424, and 426, which can be grown by performing a plurality of epitaxially growing processes. The semiconductor substrate 410 can be a silicon substrate. The III-V compound layers 422 and 426 are made of III-V compound having wide energy gap, and the III-V compound layer 424 is made of III-V compound having narrow energy gap. However, the composition of the III-V compound layers 422, 426 may be the same or different. The III-V compound layer 426 is formed on and in contact with the semiconductor substrate 410. The III-V compound layer 424 with narrow energy gap is sandwiched between the III-V compound layers 422, 426 with wide energy gap. The thickness of the III-V compound layers 422, 424, and 426 may be different.

Referring to FIG. 5, an infrared image sensor component 500 including an active pixel region 520′ formed on a semiconductor substrate 510, and a transistor 530 coupled to the active pixel region 520′ is provided. The active pixel region 520′ is the portion of a III-V compound layer stack 520 uncovered by the patterns. The III-V compound layer stack 520 is a multi-layer structure including a plurality of first III-V compound layers 522, and a plurality of second III-V compound layers 524, which can be grown by performing a plurality of epitaxially growing processes. The semiconductor substrate 510 can be a silicon substrate. The first III-V compound layers 522 are made of III-V compound having wide energy gap, and the second III-V compound layers 524 are made of III-V compound having narrow energy gap. In some embodiments, the transistor 530 is formed on the first III-V compound layer 522. The number of the first III-V compound layers 522 can be equal to the number of the second III-V compound layers 524. The first III-V compound layers 522 and the second compound layers 524 are arranged in pair, and the second III-V compound layers 522 with narrow energy gap are respectively sandwiched between the adjacent two of the first III-V compound layers 524 with wide energy gap. The thickness of the first III-V compound layers 522 and thickness of the second III-V compound layers 524 may be substantially the same (except for the uppermost layer 522).

Referring to FIG. 6, an infrared image sensor component 600 including an active pixel region 620′ formed on a semiconductor substrate 610, and a transistor 630 coupled to the active pixel region 620′ is provided. The active pixel region 620′ is the portion of a III-V compound layer stack 620 uncovered by the patterns. The III-V compound layer stack 620 is a multi-layer structure including a plurality of III-V compound layers 621, 622, 623, 624, 625, and 626. The III-V compound layers 621, 622, 623, 624, 625, and 626 are sequentially formed on the semiconductor substrate 610 by performing a plurality of epitaxially growing processes, in which the III-V compound layer 626 is in contact with the semiconductor substrate 610. The energy gap of the III-V compound layers 621, 622, 623, 624, 625, and 626 is sequentially increased, from bottom to top. Namely, the III-V compound layer 626 has the narrowest energy gap among the layers of the III-V compound layer stack 620, and III-V compound layer 621 has the widest energy gap among the layers of the III-V compound layer stack 620. The thickness of the III-V compound layers 622, 623, 624, 625, and 626 can be substantially the same and uniform. Therefore, the III-V compound layer stack 620 can be regarded as having a gradient increasing energy gap, from bottom to top.

Referring to FIG. 7, an infrared image sensor component 700 including an active pixel region 720′ formed on a semiconductor substrate 710, and a transistor 730 coupled to the active pixel region 720′ is provided. The active pixel region 720′ is the portion of a III-V compound layer stack 720 uncovered by the patterns. The III-V compound layer stack 720 is a multi-layer structure including a plurality of III-V compound layers 721, 722, 723, 724, 725, and 726. The III-V compound layers 721, 722, 723, 724, 725, and 726 are sequentially formed on the semiconductor substrate 710 by performing a plurality of epitaxially growing processes, in which the III-V compound layer 726 is in contact with the semiconductor substrate 710. The energy gap of the III-V compound layers 721, 722, 723, 724, 725, and 726 is sequentially decreased, from bottom to top. Namely, the III-V compound layer 721 has the narrowest energy gap among the layers of the III-V compound layer stack 720, and III-V compound layer 726 has the widest energy gap among the layers of the III-V compound layer stack 720. The thickness of the III-V compound layers 722, 723, 724, 725, and 726 can be substantially the same and uniform. Therefore, the III-V compound layer stack 720 can be regarded as having a gradient decreasing energy gap, from bottom to top.

Referring to FIG. 8, an infrared image sensor component 800 including an active pixel region 820′ formed on a semiconductor substrate 810, and a transistor 830 coupled to the active pixel region 820′ is provided. The active pixel region 820′ is the portion of a III-V compound layer stack 820 uncovered by the patterns. The III-V compound layer stack 820 is a multi-layer structure including a plurality of III-V compound layers 821, 822, 823, 824, 825, 826, and 827. The III-V compound layers 821, 822, 823, 824, 825, 826, and 827 are sequentially formed on the semiconductor substrate 810 by performing a plurality of epitaxially growing processes, in which the III-V compound layer 827 is in contact with the semiconductor substrate 810. The energy gap of the layers of the III-V compound layer stack 820 is sequentially decreased, from bottom to middle, and energy gap of the layers of the III-V compound layer stack is sequentially increased, from middle to top. Namely, the III-V compound layer 824 at the middle of the III-V compound layer stack 820 may have the narrowest energy gap among the layers of the III-V compound layer stack 820. The III-V compound layer 821, and 827 at opposite sides of the III-V compound layer stack 820 may have the widest energy gap among the layers of the III-V compound layer stack 820.

Referring to FIG. 9, an infrared image sensor component 900 including an active pixel region 920′ formed on a semiconductor substrate 910, and a transistor 930 coupled to the active pixel region 920′ is provided. The active pixel region 920′ is the portion of a III-V compound layer stack 920 uncovered by the patterns. The III-V compound layer stack 920 is a multi-layer structure including a first III-V compound layer 922 and a second III-V compound layer 924, in which the second III-V compound layer 924 is disposed between the first III-V compound layer 922 and the semiconductor substrate 910. The energy gap of the first III-V compound layer 922 is different from that of the second III-V compound layer 924 thereby forming a 2DEG layer therebetween. The thickness of the first III-V compound layer 922 is thinner than that of the second III-V compound layer 924. The energy gap of the first III-V compound layer 922 is substantially consistent since the energy gap of the second III-V compound layer 924 is in a gradient distribution. In some embodiment, the energy gap of the second III-V compound layer 924 is gradually increased from top to bottom. Namely, the portion of the second III-V compound layer 924 close to the first III-V compound layer 922 has a smaller energy gap since the portion of the second III-V compound layer 924 close to the semiconductor substrate 910 has a larger energy gap.

Referring to FIG. 10, an infrared image sensor component 1000 including an active pixel region 1020′ formed on a semiconductor substrate 1010, and a transistor 1030 coupled to the active pixel region 1020′ is provided. The active pixel region 1020′ is the portion of a III-V compound layer stack 1020 uncovered by the patterns. The III-V compound layer stack 1020 is a multi-layer structure including a first III-V compound layer 1022 and a second III-V compound layer 1024, in which the second III-V compound layer 1024 is disposed between the first III-V compound layer 1022 and the semiconductor substrate 1010. The energy gap of the first III-V compound layer 1022 is different from that of the second III-V compound layer 1024 thereby forming a 2DEG layer therebetween. The thickness of the first III-V compound layer 1022 is thinner than that of the second III-V compound layer 1024. The energy gap of the first III-V compound layer 1022 is substantially consistent since the energy gap of the second III-V compound layer 1024 is in a gradient distribution. In some embodiment, the energy gap of the second III-V compound layer 1024 is gradually decreased from top to bottom. Namely, the portion of the second III-V compound layer 1024 close to the first III-V compound layer 1022 has a larger energy gap since the portion of the second III-V compound layer 1024 close to the semiconductor substrate 1010 has a smaller energy gap.

Referring to FIG. 11, an infrared image sensor component 1100 including an active pixel region 1120′ formed on a semiconductor substrate 1110, and a transistor 1130 coupled to the active pixel region 1120′ is provided. The active pixel region 1120′ is the portion of a III-V compound layer stack 1120 uncovered by the patterns. The III-V compound layer stack 1120 is a multi-layer structure including a first III-V compound layer 1122 and a second III-V compound layer 1124, in which the second III-V compound layer 1124 is disposed between the first III-V compound layer 1122 and the semiconductor substrate 1110. The energy gap of the first III-V compound layer 1122 is different from that of the second III-V compound layer 1124 thereby forming a 2DEG layer therebetween. The thickness of the first III-V compound layer 1122 is thinner than that of the second III-V compound layer 1124. The energy gap of the first III-V compound layer 1122 is substantially consistent since the energy gap of the second III-V compound layer 1124 is in a gradient distribution. In some embodiment, the energy gap of the second III-V compound layer 1124 is gradually decreased from top to middle, and is further gradually increased from middle to bottom. Namely, the portions of the second III-V compound layer 1124 close to the first III-V compound layer 1122 and close to the semiconductor substrate 1110 have a larger energy gap since the middle portion of the second III-V compound layer 1124 has a smaller energy gap.

The infrared image sensor component includes at least one III-V compound layer on the semiconductor substrate, in which the portion of the III-V compound layer(s) uncovered by the patterns is utilized as active pixel region for detecting the incident infrared ray. The infrared image sensor component includes at least one transistor coupled to the active pixel region, and charge generated by the active pixel region is transmitted to the transistor. The III-V compound material has wider infrared wavelength coverage than the silicon, larger absorption coefficient in the infrared region than the silicon, and higher carrier mobility than the silicon, thus performance of the infrared image sensor component is improved accordingly.

According to some embodiments of the disclosure, a method includes epitaxially growing a first III-V compound layer over a semiconductive substrate; epitaxially growing a second III-V compound layer over the first III-V compound layer; forming a source/drain contact over the second III-V compound layer; forming a gate structure over the second III-V compound layer; and forming a pattern shielding the gate structure and the source/drain contact, wherein a portion of the second III-V compound layer is free from coverage by the pattern.

According to some embodiments of the disclosure, a method includes epitaxially growing a first III-V compound layer over a semiconductive substrate; forming a source/drain contact over the first III-V compound layer; and forming a gate structure over the first III-V compound layer. The first III-V compound layer has an energy gap in a gradient distribution.

According to some embodiments of the disclosure, a method includes epitaxially growing a first III-V compound layer over a semiconductive substrate; forming a source/drain contact over the first III-V compound layer; after forming the source/drain contact, forming a gate structure over the first III-V compound layer; and forming a pattern shielding the gate structure and the source/drain contact. A portion of the first III-V compound layer is free from coverage by the pattern.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A method, comprising: epitaxially growing a first III-V compound layer over a semiconductive substrate; epitaxially growing a second III-V compound layer over the first III-V compound layer; forming a source/drain contact over the second III-V compound layer; forming a gate structure over the second III-V compound layer; and forming a pattern shielding the gate structure and the source/drain contact, wherein a portion of the second III-V compound layer is free from coverage by the pattern.
 2. The method of claim 1, wherein the first III-V compound layer and the second III-V compound layer have different energy gaps.
 3. The method of claim 1, further comprising: epitaxially growing a third III-V compound layer over the first III-V compound layer prior to epitaxially growing the second III-V compound layer over the first III-V compound layer.
 4. The method of claim 3, wherein the first III-V compound layer and the third III-V compound layer have different energy gaps.
 5. The method of claim 1, wherein forming the source/drain contact is performed prior to forming the gate structure.
 6. The method of claim 1, wherein forming the source/drain contact over the second III-V compound layer comprises: depositing a dielectric layer over the second III-V compound layer; etching the dielectric layer to form a first opening; and filling the first opening with the source/drain contact.
 7. The method of claim 6, wherein forming the gate structure over the second III-V compound layer comprises: etching the dielectric layer to from a second opening; and filling the second opening with the gate structure.
 8. The method of claim 7, wherein etching the dielectric layer to from the second opening is performed after filling the first opening with the source/drain contact.
 9. A method, comprising: epitaxially growing a first III-V compound layer over a semiconductive substrate, wherein the first III-V compound layer has an energy gap in a gradient distribution; forming a source/drain contact over the first III-V compound layer; and forming a gate structure over the first III-V compound layer.
 10. The method of claim 9, wherein the energy gap of the first III-V compound layer is gradually increased from a top surface to a bottom surface of the first III-V compound layer.
 11. The method of claim 9, wherein the energy gap of the first III-V compound layer is gradually decreased from a top surface to a bottom surface of the first III-V compound layer.
 12. The method of claim 9, further comprising: epitaxially growing a second III-V compound layer over the first III-V compound layer prior to forming the source/drain contact over the first III-V compound layer.
 13. A method, comprising: epitaxially growing a first III-V compound layer over a semiconductive substrate; forming a source/drain contact over the first III-V compound layer; after forming the source/drain contact, forming a gate structure over the first III-V compound layer; and forming a pattern shielding the gate structure and the source/drain contact, wherein a portion of the first III-V compound layer is free from coverage by the pattern.
 14. The method of claim 13, further comprising: forming a doped III-V compound layer over the first III-V compound layer; and etching the doped III-V compound layer to form a doped III-V compound region over the first III-V compound layer.
 15. The method of claim 14, wherein forming the gate structure is performed such that the gate structure is directly over the doped III-V compound region.
 16. The method of claim 14, wherein forming the source/drain contact is performed such that the source/drain contact is spaced apart from the doped III-V compound region.
 17. The method of claim 14, further comprising: depositing a dielectric layer over the first III-V compound layer and the doped III-V compound region; and etching the dielectric layer to form a first opening that exposes the doped III-V compound region, wherein forming the gate structure is performed such that the gate structure is formed in the first opening.
 18. The method of claim 17, further comprising: etching the dielectric layer to form a second opening, wherein forming the source/drain contact is performed such that the source/drain contact is formed in the second opening.
 19. The method of claim 18, wherein etching the dielectric layer to form the second opening is performed prior to etching the dielectric layer to form the first opening.
 20. The method of claim 14, further comprising: epitaxially growing a second III-V compound layer over the first III-V compound layer prior to forming the doped III-V compound layer. 